Mr. S. P. Badar

Mr. S. P. Badar

Assistant Professor
Email/Mobile No. :Email: spbadar@ssgmce.ac.in
Phone:9503733768
ACADEMIC QUALIFICATION

Ph.D.(Pursuing), M.E. (Electronics Engineering), B.E.(Electronics & Telecommunication Engg)
AREA OF SPECIALIZATION VLSI Design
EXPERIENCE

 Teaching: 13 Years
 Industrial: 1.5 Years
COURSES TAUGHT
  • VLSI Design
  • CMOS Design
  • Network Analysis / Network Theory
  • Digital Electronics
  • Electronics Devices & Circuits
  • Electronics Devices & Components
ORCID ID/ SCOPUS ID/ Web of Science ID/ VIDWAN ID/ RESEARCHER ID/Google Scholar ID:
MEMBERSHIP
  • IEEE Graduate Student Member (Member ID- 97548153) –Annual
  • IEEE Young Professionals
  • IEEE Robotics and Automation Society Membership
  • IEEE SIGHT
PUBLICATIONS
  • S.P. Badar, K. B. Khanchandani, P. R. Wankhede, A Brief Study of Successive Cancellation Polar Decoder- Design and Performance Analysis SSGM Journal of Science and Engineering, Vol. 1 No. 1 (2023) Proceedings of INSCIRD-2023, pp.-146-150
  • S. P. Badar, K. Khanchandani and P. Wankhede, Fast Polar Decoder Implementation using Special Nodes, 2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS), Nagpur, India, 2023, pp. 1-6, doi: 10.1109/PCEMS58491.2023.10136054.
  • S. P. Badar and K. Khanchandani, Successive Cancellation Polar Decoder Implementation using Processing Elements, 2022 IEEE Region 10 Symposium (TENSYMP), Mumbai, India, 2022, pp. 1-6, doi: 10.1109/TENSYMP54529.2022.9864529.
  • S. P. Badar and K. Khanchandani, Implementation of Combinational Logic for Polar Decoder, 2021 2nd International Conference on Range Technology (ICORT), Chandipur, Balasore, India, 2021, pp. 1-6, doi: 10.1109/ICORT52730.2021.9581844.
RESEARCH AND DEVELOPMENT
  • To design and implement fast polar code decoder for 5G wireless application.
  • 1024 bit Fast Simplified Successive Cancellation Polar Decoder is designed.
  • S.P. Badar, K. B. Khanchandani, P. R. Wankhede, A Brief Study of Successive Cancellation Polar Decoder: Design and Performance Analysis, SSGM Journal of Science and Engineering, Vol. 1 No. 1 (2023): Proceedings of INSCIRD-2023, pp.-146-150
RESEARCH GUIDANCE
FDP/STTP/Workshop/Training Programme Attended / Organized
FELLOWSHIP / AWARD
  • Summer Faculty Research Fellowship at IIT Delhi during 17th May 2023 to 08th July 2023.
  • Best Paper Award for the paper Implementation of Combinational Logic for Polar Decoder at 2nd IEEE International Conference on Range Technology (ICORT-2021) during 5th -6th August 2021.
  • Certification for Training in Advanced Capabilities in Electronics Design and Manufacturing (TRIAC-EDM) by NIELIT, India and III Taiwan- 2020-21.
  • Summer Faculty Research Fellowship (Online) at IIT Delhi during 1st June 2020 to 31st July 2020.
  • Secured 2nd rank for the project Design and Development of Analog Circuits using Unconventional CMOS Techniques for Biomedical Applications at National level Cadence Design Contest at Bangalore in Jan 2019.
OTHER

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